Built-in self-test technique for read-only memories

ABSTRACT

Self-testing of a read only memory (10&#39;) containing an m×n+1 array of single-bit storage cells (12&#39;) is accomplished by first loading the bits of a preselected quotient string into the n+0 column of the memory. The quotient string is typically preselected to yield an all-zero residue if no errors are present. Thereafter, a first polynomial division is performed on the entire contents of the memory by sequentially shifting out of the bits in the cells in each successive ROM row in a right-to-left direction into a separate one of the n+1 inputs of a bidirectional multiple input shift register (18&#39;). A second polynomial division is then performed on the m×n contents of the memory (10&#39;) by sequentially shifting the bits out of each successive row into the shift register (18&#39;) in a left-to-right direction. As each row of bits is shifted into the shift register (18&#39;) during the second polynomial division, the register generates a quotient bit which is exclusively OR&#39;d with a corresponding one of the quotient bits stored in the n+1 th  column of the memory, allowing for errors in the memory to be detected. At the conclusion of the second polynomial division, there remains in the register a residue, also indicative of the errors in the memory.

TECHNICAL FIELD

This inventin relates to a technique for built-in self-testing of aRead-Only Memory (ROM) to verify its operation.

BACKGROUND OF THE INVENTION

Much effort is now being devoted toward designing digital electroniccircuits which have the built-in capability of being "self-testing,"that is, the ability to test their internal operation without the needfor specialized test equipment. Developing a built-in self-testcapability for a complex digital circuit containing separate structuralelements is difficult because each different functional element oftenoperates in a different manner. To simplify this task, many circuitdesigners use a "divide and conquer" strategy which entails developing aseparate self-test routine for testing each separate structural elementof the circuit.

To achieve complete self-testing of a complex digital circuit containinga read-only memory (ROM) comprised of an m×n matrix array of storagelocations, a self-testing technique for the ROM is thus required.Presently, self-testing of a ROM is frequently accomplished by atechnique known as "signature analysis". Signature analysis of a ROM isaccomplished by sequentially shifting the stored bit out of each of then cells in each successive one of the m rows of the ROM into a separateone of the inputs of a multiple input shift register (MISR) whose outputis fed back to its input. As each bit is shifted into the correspondingone of the MISR inputs, the MISR exclusively OR's the bit with the bitpreviously received from the preceding column in the preceding row.

The bits of a selected sub-set of the exclusively OR'd bits arethemselves exclusively OR'd and then fed back into the MISR input toenable the MISR to effectively perform a polynomial division on the ROMcontents. At the completion of the polynomial division, there remains inthe MISR a string of n bits which represents the remainder from thepolynomial division and used as an indicator of the operation of theROM. From a comparison of the actual residue to a reference value (whichcorresponds to the value of the residue when no faults are present), adetermination can be made as to whether the ROM is faulty.

The advantage of the signature analysis technique for self-testing of aROM is that the residue which remains in the MISR (representing the"signature" of the ROM) is only n bits long. Thus, by using signatureanalysis, the m×n bits of data stored in the ROM are effectivelycondensed or compacted into an n bit string. Consequently, if allpossible error patterns are assumed to be equally likely, thepossibility of error escape is 2^(-n). Although the likelihood of errorescape using the conventional signature analysis may seen small, even asmall likelihood of error is undesirable for high quality faultcoverage. The error escape which occurs during conventional signatureanalysis is attributable to error masking and error cancellation. Errorcancellation can occur each time each of a successive row of bits of theROM is shifted into the MISR and is exclusively OR'd with the bit in thepreceding column in the preceding row of the ROM thus, compacting them×n bit ROM contents into an m+n-1 string. The bits which areexclusively OR'd in this manner are thus diagonally adjacent, and ifeach is erroneous, the errors tend to cancel each other out during thepolynomial division. Consequently, the residue remaining in the MISR maynot reflect the presence of an even number of erroneous, diagonallyadjacent bits. Error masking arises from the compaction of the m×n-1string into the n bit residue in the MISR. The compaction of the m×nbits in the ROM into an n bit MISR residue is effectively an m-to-1mapping process. Failure to map one or more erroneous bits may give riseto an undetected error.

Therefore, there is a need for a self-test technique for a ROM whichaffords reduced incidence of error masking and error cancellation.

SUMMARY OF THE INVENTION

Briefly, in accordance with a preferred embodiment of the invention, atechnique is provided for self-testing a ROM containing an m×n+1 bitarray of storage cells, the n+1^(th) column containing a separate one ofa set of predetermined bits effectively leaving the remaining m×n arrayof cells available for conventional data storage. The first step is toperform a first polynomial division on the entire contents of the ROM bysequentially shifting each of the n+1 bits in each successive row into aseparate one of the n+1 inputs of a bidirectional multiple input shiftregister (MISR) in a right-to-left direction. Thereafter, a secondpolynomial division is performed on the m×n contents of the ROM bysequentially shifting each of the first n bits in each successive row inthe ROM into a separate one of the first n inputs of the MISR in aleft-to-right direction. During the second polynomial division, the MISRproduces a quotient bit after each of the first n bits in eachsuccessive row of the ROM is shifted into the MISR. Each successivequotient bit is exclusively OR'd with the bit stored in a successive oneof cells in the n+1^(th) ROM column, which is precalculated such thatwhen exclusively OR'd with each successive quotient bit from the MISR, azero results if no defect is present in the row of ROM bits. At thecompletion of the second polynomial division, the bits remaining in theMISR, (i.e., the residue) may be shifted out for comparison to apredetermined value representative of the expected MISR residue when nodefects are present.

The above-described technique eliminates the incidence of error masking.By exclusively OR'ing the quotient produced by the MISR during eachcycle of the second polynomial division with a successive one of thepre-calculated quotient bits in the n+1^(th) column of the ROM, theeffective length of the ROM signature becomes m+n-1 bits long. Theincreased length of the effective ROM signature results in no errormasking since essentially no information is lost during the mapping ofthe m×n ROM bits into the ROM signature.

Error cancellation is greatly reduced by the present self-testingtechnique because the data in each row of the ROM is shifted into theMISR in opposite directions during each cycle of the first and secondpolynomial division, respectively. As a consequence, an even number oferroneous bits which lie on the same diagonal are unlikely to canceleach other as would otherwise occur if only a single polynomial divisionwere performed.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block schematic diagram of an m×n bit, read-only memory(ROM) which is self-tested using a conventional signature analysistechnique;

FIG. 2 is a block diagram of a m×n+1 bit ROM which is self-tested inaccordance with the technique of the present invention; and

FIG. 3 is a flowchart diagram illustrating the manner in which the ROMof FIG. 2 is self-tested in accordance with the technique of theinvention.

DETAILED DESCRIPTION

Before proceeding to describe the built-in self-test technique of thepresent invention, a thorough understanding of a conventional read-onlymemory (ROM) 10, as depicted schematically in FIG. 1, will provehelpful. The ROM 10 is comprised of plurality of storage cells 12arranged in a matrix array of m rows by n columns, where m and n areintegers. For purposes of illustration, the ROM 10 is comprised of a 4×9array of cells 12 although ROMs having a greater or lesser number ofcells are indeed possible. In practice, the number of rows in the ROM 10usually exceeds the number of columns. Each individual storage cell 12,which stores a single bit of data, may be referenced as 12_(i),j where iand j are integers which identify the particular row and columncoordinates, respectively, of the cell. The ROM 10 also includes aninput register/decoder 14 which, when supplied with the address of thej^(th) cell 12 in the i^(th) row, causes the bit stored in the cell tobe output on the j^(th) one of a set of output lines 15₁, 15₂, 15₃ . . .15_(n) of the ROM 10.

Conventional self-testing (signature analysis) of the ROM 10 is carriedout with the aid of a counter 16 and a multiple input shift register(MISR) 18. The counter 16 supplies the register/decoder 14 with amonotonically increasing count indicative of the address of a successiverow of storage cells 12 in the ROM 10 whose stored bits are to be outputon a corresponding one of the ROM output lines 15₁, 15₂, 15₃ . . .15_(n), respectively.

The multiple input shift register 18 is comprised of n flip flops 20₁,20₂, 20₃ . . . 20_(n) arranged in a daisy chain. Each of the flip-flops20₁, 20₂, 20₃ . . . 20_(n) has its output coupled to a first input of aseparate one of a set of exclusive OR gates 22₁, 22₂, 22₃ . . .22_(n-1), respectively, each gate having its output coupled to the inputof a separate one of the flip-flops 20₂, 20₃, 20₄ . . . 20_(n),respectively. Each of the exclusive OR gates 22₁, 22₂, 22₃ . . .22_(n-1) has a second input coupled to a separate one of the ROM outputlines 15₂, 15₃, 15₄ . . . 15_(n), respectively.

The flip-flop 20₁ is supplied with the output signal of an exclusive ORgate 22_(n) which has three inputs. The first of the three inputs of theexclusive OR gate 22_(n) is supplied with the signal on the ROM outputline 15₁ while the second of the gate inputs is supplied with the outputof the flip-flop 20_(n). The third of the inputs of the exclusive ORgate 22_(n) is supplied with the output signal of a selected group ofthe flip-flops 20₁, 20₂, 20₃ . . . 20_(n) as supplied via a set ofexclusive OR gates 24. The particular group of the flip-flops 20₁, 20₂,20₃ . . . 20_(n), whose output signals are exclusively OR'd before beingsupplied to the exclusive OR gate 22_(n), is selected such that thesignals fed back to the flip-flop 20₁ form a "primitive" polynomial,which establishes the divisor for the polynomial division performed bythe MISR 18. A primitive polynomial causes the MISR 18 to generate 2^(n)-1 separate residues when no input is present at the MISR whereas anon-primitive polynomial causes the MISR to generate less than 2^(n) -1separate residues.

Conventional self-testing (signature analysis) of the ROM 10 is carriedout by initializing the counter 16 with the address of the rowcontaining the cell 12₁,1. The counter 16 then counts upward, therebysupplying the register/decoder 14 with the address of successive one ofthe rows of the ROM 10. Upon receipt of the address of a particular row,the bits stored in the cells 12 in the row are output on thecorresponding one of the ROM output lines 15₁, 15₂, 15₃ . . . 15_(n) forinput into a corresponding one of the exclusive OR gates 22_(n), 22₁,22₂ . . . 22_(n-1).

The process of shifting out the stored bits in each row in the ROM 10into a separate one of the n inputs of the MISR 18 is repeated until thebits in the last row of the ROM are shifted out to the MISR. The effectof shifting the bits of each successive row of the ROM 10 into the MISR18 (when configured as described) is to perform a polynomial division onthe contents of the ROM, with the divisor being a polynomial establishedby the particular combination of the flip-flops 20₂, 20₃ . . . 20_(n)whose output signals are fed back to the flip-flop 20₁ through theexclusive OR gates 24. The remainder from the polynomial divisionperformed by the MISR 18 is the residue, i.e., the bits remaining in theflip-flops 20₁, 20₂, 20₃ . . . 20_(n). The successive bit output by thelast flip-flop 20_(n) in the MISR 18 after each row of bits has beenshifted into the MISR 18 represents a successive one of the bits in aquotient string (i.e., the quotient of the polynomial division) which istypically ignored in conventional signature analysis.

The residue in the MISR 18 after the polynomial division on the m×ncontents of the ROM 10 is indicative of the operation of the ROM 10.Since, by their nature, the contents of the ROM 10 are expected toremain static once entered into it, the value of the residue remainingin the MISR 18 after the polynomial division should remain the same eachtime unless an error is present. By comparing the actual residue in theMISR 18 after the polynomial division is completed to a known valuerepresenting the expected residue for a defect-free ROM 10 (i.e., onewhose bits are all correct), the errors, if any, in the ROM can beuncovered.

Self-testing of the ROM 10 by conventional signature analysis, asdescribed above, is prone to two types of error escape. The first typeof error escape is known as error cancellation. Error cancellationoccurs because, as the bits in each successive row of the ROM 10 areshifted into the MISR 18, each bit is exclusively OR'd with the bit inthe cell 12 in the immediately preceding column in the preceding rowwhich is diagonally adjacent thereto thus compacting the m×n bits intoan m+n-1 bit string. A better understanding of this phenomenon may behad by reference to Table I which illustrates how such errorcancellation may occur within the 4×9 ROM 10 of FIG. 1.

                  TABLE I                                                         ______________________________________                                        0    1     1     0   1   1   0   1   1                                                                 ROM 10                                                                                    rows                                                               0 0 1 0 .0. 1 0 1                                                              0 1 0 0 0 1 0 1 0                                                              0 1 1 .0. 0 1 0 1 1                                                        0 1 1 0 0 1  -0 1 0 0 1 1                            ______________________________________                                    

Each of the first four rows in the table represents each successive oneof the four rows of bits of stored in the ROM 10 as they are shiftedinto the MISR 18. Each succeeding one of the first four rows in Table Iis offset to the right of the row above it by one bit. The reason whyeach successive row is offset by one bit from each preceding one isbecause as each bit is output on a ROM line 15_(i) and enters the MISR18, the bit is added to the bit received on the ROM line 15_(i-1) fromthe previous row. The last row of bits in the table represents the sumobtained by exclusiving OR'ing of the rows of ROM bits (as offset in themanner just described), so that the total number of bits in the last rowwill be m+n-1. The last row in Table I represents the dividend for thepolynomial division performed by the MISR 18.

To appreciate the problem of error cancellation, assume that twodiagonally adjacent bits in the ROM 10 erroneously appear as a zero,rather than a one, as indicated by those two "1" bits in Table I whichare overstruck by a "0". Because of the one-bit offset between the rowsof ROM bits as they are shifted into the MISR 18, the two diagonallyadjacent, erroneous bits appear in the same column in Table I. Thus,when both of these diagonally adjacent bits are erroneously a "0", theresultant residue (obtained by exclusively OR'ing the bits in each ofthe first nine columns) will be the same because the two erroneous bitswill cancel each other out. Thus, the resultant residue of the MISR 18will remain the same even when these two ROM bits are erroneous.

Another type of error escape that occurs is known as error masking.Error masking arises when the m+n-1 string obtained by exclusivelyOR'ing the rows of ROM bits is compacted into an n bit residue duringpolynomial division. As a result of this compaction, some of the bits ofthe ROM signature are lost, and any errors contained in them will thusbe masked.

Referring now to FIG. 2, there is shown a system 26' in accordance withthe present invention, for self-testing a read-only memory 10' (ROM)with reduced incidence of error masking and error cancellation. The ROM10' is configured of a matrix array of storage cells 12' and aregister/decoder 14' for addressing an individual one of the storagecells just like the ROM 10 of FIG. 1. The only distinction between theROM 10 of FIG. 1 and the ROM 10' of FIG. 2 is that the array of storagecells 12' is of a size m×n+1, with the n+1^(th) column of storage cellsbeing employed to store data used in self-testing of the ROM as will bedescribed later. Thus, while the ROM 10' contains an extra column ofstorage cells 12', its effective capacity for storing application datais only m×n bits, the same as the ROM 10 of FIG. 1. The bits stored in aseparate one of the cells 12' in each row of ROM 10' (including those inthe n+1^(th) column) are output on a separate one of a set of ROM outputlines 15'₁, 15'₂, 15'₃ . . . 15'_(n) and 15'_(n+1), respectively, whenthe corresponding address of the cell is applied to the register/decoder14'

The system 26' of the invention for self-testing the ROM 10' iscomprised of a counter 16' identical to the counter 16 of FIG. 1, and abidirectional multiple input shift register (MISR) 18'. The MISR 18' isconfigured differently than the MISR 18. In particular, the MISR 18' isconfigured of n+1 flip-flops 20'₁, 20'₂, 20'₃ . . . 20'_(n+1) connectedin daisy chain fashion. Each of the flip-flops 20'₁, 20'₂, 20'₃ . . .20'_(n-1) has its output coupled to a first input of a separate one of aset of multiplexers 21'₁, 21'₂, 21'₃ . . . 21'_(n-1), respectively, eachmultiplexer having its output coupled to a first input of a separate oneof a set of exclusive OR gates 22'₁, 22'₂, 22'₃ . . . 22'_(n-1),respectively. The exclusive OR gates 22'₁ , 22'₂, 22'₃ . . . 22'_(n-1)each have a second input coupled to a separate one of the output lines15'₁, 15'₂, 15'₃ . . . 15'_(n), respectively, of the ROM 10'. The outputof each of the exclusive OR gates 22'₁, 22'₂, 22'₃ . . . 22'_(n-1) iscoupled to the input of a separate one of the flip-flops 20'₂, 20'₃,20'₄ . . . 20'_(n), respectively.

The flip-flop 20'_(n) of the MISR 18' has its output coupled to a firstinput of an exclusive OR gate 22'_(n) whose second input is coupled tothe ROM output line 15'_(n+1). The exclusive OR gate 22'_(n) has itsoutput coupled to a first input of a conventional OR gate 23' whosesecond input is supplied of the output of the flip-flop 20'_(n+1). Theoutput of the OR gate 23' is supplied to a first input of a multiplexer21'_(n) whose output feeds the input of the flip-flop 20'_(n+1).

The flip-flop 20'₁ is supplied at its input with the output of anexclusive OR gate 22'_(n+1) having a first input coupled to the ROMoutput line 15'₁. The exclusive OR gate 22'_(n+1) has a second inputcoupled to the output of a multiplexer 21'_(n+1) having a first inputsupplied with the output of a particular group of the flip-flops 20'₂,20'₃ . . . 20'_(n), via a set of exclusive OR gates 24' so as to providethe MISR 18' with a "primitive" feedback polynomial. The feedback signalsupplied to the second input of the multiplexer 21'_(n+1) is alsosupplied to a first input of an exclusive OR gate 22_(n+2) whose secondinput is supplied with the signal on the line 15'_(n+1). The output ofthe exclusive OR gate 22_(n+2) is supplied to the second input of the ORgate 23'.

As thus described, each flip-flop 20'_(p) has its output coupled througha corresponding multiplexer 21'_(p) and an exclusive OR gate 22'_(p) tothe next downstream flip-flop 20'_(p+1), where p is an integer 1,2,3 . .. n. In this way, the bit latched in the flip-flop 20'_(p) isexclusively OR'd with the bit from the next row of the ROM on the ROMoutput line 15'_(p+1) before being input to the downstream flip-flop20'_(p+1) as occurs during the operation of the MISR 18 of FIG. 1. Thus,the MISR 18' of FIG. 2 is operative to receive the bits shifted out ofthe ROM 10' on the ROM output lines 15'₁, 15'₂, 15'₃ . . . 15'_(n) in aleft-to-right direction in the same manner as the MISR 18 of FIG. 1.

However, unlike the MISR 18 of FIG. 1, the MISR 18' can also operate toreceive the bits shifted out of the ROM 10 on the output lines15'_(n+1), 15'_(n), 15'_(n-1), 15'_(n-2) . . . 15'₁ in a right-to-leftdirection. To allow for data to be shifted into the MISR 18' in theright-to-left direction, the second input of each of the multiplexers21'₁, 21'₂, 21'₃, 21'₄ . . . 21'_(n-2) is supplied with the output of aseparate one of the flip-flops 20'₃, 20'₄, 20'₅ . . . 20'_(n),respectively. In this way, the output of a separate one of theflip-flops 20'_(n+1), 20'_(n), 20'_(n-1), 20'_(n-2) . . . 20'₃ can besupplied to the input of a respective one of the flip-flops 20'_(n),20'_(n-1), 20'_(n-2) . . . 20'₁. For example, a bit on the ROM outputline 15'_(n+1), which has been shifted into the flip-flop 20'_(n+1), canthen be input to the exclusive OR gate 22'_(n-1), together with the biton the ROM line 15_(n), in order to shift a bit into the flip-flop20'_(n). Similarly, the bit shifted into the flip-flop 20'_(n) andoutput thereby will be input, via the multiplexer 21'_(n-2) and theexclusive OR gate 21_(n-1), to the flip-flop 20'_(n-1) and so on. Byappropriately controlling the multiplexers 21'₁, 21'₂, 21'₃ . . .21'_(n), the bits appearing on the output lines 15'_(n+1), 15'_(n),15'_(n-1), 15'_(n-2) . . . 15'₁ of the ROM 10' can be shifted in aright-to-left direction into the flip-flops 20'_(n+1), 20'.sub. n,20'_(n-1) . . . 20'₁.

Referring to FIG. 3, there is shown a flow chart diagram illustratingthe steps executed to self-test the ROM 10' of FIG. 2. The first step28' in the process is to load an initial value (a "seed") into the MISR18' in preparation to performing two successive polynomial divisions onthe contents of the ROM 10'. The value of the seed is selected so thatafter both a first polynomial division is performed on the m×n+1contents of the ROM 10' and a second polynomial division is performed onthe m×n ROM contents, the residue of the MISR 18' will be all zeros.

To establish the value of the seed, five successive polynomial divisions(stages) are performed, each polynomial division being performed bysimulating the shifting of successive strings of bits into the MISR 18'.The first polynomial division is performed on a dividend consisting ofthe m×n contents of the ROM 10' (excluding the n+1^(th) column ofcells). Thus, the first polynomial division is performed by simulatingthe shifting of successive rows of zeros into the MISR 18'. The divisorpolynomial (P₁) for the first stage division is chosen to be identicalto the actual polynomial divisor of the MISR 18' of FIG. 2, whichresults upon the actual shifting of the bits in each successive row theROM 10' into the MISR in a right-to-left direction. The seed (initialMISR contents) for the first stage polynomial division is chosen to be astring of zeros. Upon completion of the first stage polynomial division,a residue, (designated as the string S₁) is produced. The quotientstring (e.g., the successive bits produced by the right-hand mostflip-flop (20'₁) each time a successive row of bits is shifted into theMISR 18) is simply ignored.

Following the first stage polynomial division, a second stage polynomialdivision is then performed, again by simulating the shifting of stringsof bits into the MISR 18' in a right-to-left direction. The dividend ischosen as all zeros while the polynomial divisor (P₂) is chosen to bethe reciprocal of P₁. The seed for the second stage polynomial divisionis chosen as S₁, the residue remaining after the first stage polynomialdivision. At the completion of the second stage polynomial division, aresidue S₂ remains. As before, the quotient string is simply ignored.

The second stage polynomial division is followed by a third stagepolynomial division during which the m×n contents of the ROM 10' aredivided by the polynomial P₁. This division, like the two which precededit, is preformed by simulating the shifting of strings of bits into theMISR 18' in a right-to-left direction. The seed for the third stagepolynomial division is the string S₂, the residue of the second stagedivision. The residue (S₃) at the completion of the third stagepolynomial division will be a string of zeros. The quotient string (q)produced during the third stage division is saved and serves as thepredetermined bit string which is loaded into the n+1^(th) column of theROM 10'.

A fourth stage polynomial division is next performed on the m×n+1contents of the ROM 10' by simulating the shifting of strings of bitsinto the MISR 18' in a left-to-right direction. The polynomial divisor(P₃) for the fourth stage polynomial division is the same as the actualpolynomial divisor of the MISR 18' of FIG. 2 which occurs upon theshifting of the bits of each successive row of the ROM 10' into the MISRin a left-to-right direction. A string of all zeros is employed as theseed for the fourth stage polynomial division. At the completion of thefourth stage polynomial division, a residue S₄ is produced. Successivebits of a quotient string will also be output by the left-hand mostflip-flop (20'_(n+1)) but these bits are ignored during this division.

After the fourth stage polynomial division, a fifth stage polynomialdivision is performed on a dividend consisting of all zeros in the samemanner as during the fourth division. The polynomial divisor (P₄) forthis division is the reciprocal of the polynomial P₃. The seed for thisdivision is the exclusive sum of the residues S₂ and S₄ (obtained byexclusively OR'ing the S₂ and S₄). Following the fifth stage polynomialdivision, a residue S₅ remains. It is the residue S₅ which serves forthe initial seed loaded into the MISR 18' during step 28'.

Referring to FIG. 3, following step 28', step 30' is executed, at whichtime, a first polynomial division is performed on the m×n+1 contents ofthe ROM 10' of FIG. 2. The first polynomial division is carried out bycausing the counter 16' to address the n+1 bits in each of the m rows ofthe ROM 10'. In this way, the bits stored in each row of the ROM 10' areoutput on the ROM output lines 15'_(n+1), 15'_(n), 15'_(n-1) . . . 15'₁.During this time, each of the multiplexers 21'₁, 21'₂, 21'₃ . . .21'_(n) within the MISR 18' of FIG. 2 is operated such that eachmultiplexer only feeds the signal of a separate one of the flip-flops20'₃, 20'₄, 20'₅ . . . 20'_(n+1) to a respective one of the flip-flops20'₂, 20'₃, 20' ₄ . . . 20'_(n). In this way, the bit appearing on aseparate one of the ROM output lines 15'_(n+1), 15'_(n), 15'_(n-1) . . .15'₁ can be shifted into a respective one of the flip-flops 20'_(n+1),20'_(n), 20'_(n-1) . . . 20'₁ in a right-to-left direction.

The process of shifting out the n+1 bits in each successive row of theROM 10' continues until the bits of the m^(th) row have been shiftedinto the MISR 18', at which time, the first polynomial division iscompleted. At the completion of the first polynomial division, thereremains in the MISR 18' a residue representing a "signature" of the ROM10'. This signature is allowed to remain in the MISR 18'. During theprocess of performing the first polynomial division on the entirecontents of the ROM 10', the flip-flop 20'₁ will generate a successiveone of the bits of a quotient bit string during each cycle of thepolynomial division (i.e., during the shifting of each row of bits intothe MISR). The bits in the quotient bit string generated during thefirst polynomial division are ignored.

Following step 30', step 32' is executed and a second polynomialdivision is performed, this time on only the m×n contents of the ROM10'. In other words, the bits in the n+1^(th) column are excluded. Thesecond polynomial division is carried out by causing the counter 16' ofFIG. 2 to address each of the first n bits in each successive row of theROM 10' so that the bits appear on the ROM output lines 15'₁, 15'₂, 15'₃. . . 15'_(n). During this time, the multiplexers 21'₁, 21'₂, 21'₃ . . .21'_(n) within the MISR 18' are operated such that each only passes theoutput signal from its corresponding upstream flip-flop 20'₁, 20'₂, 20'₃. . . 20'_(n-1) to the flip-flop immediately downstream therefrom. Inthis way, the bits in each of the m rows of the ROM 10' are shifted intothe MISR 18' in a left-to-right direction.

The shifting of the first n bits in each successive row of the ROM 10'continues until the bits in the last row of the ROM have been shiftedinto the MISR 18. As the n bits in each ROM row are shifted into theMISR 18', the flip-flop 20'_(n) generates a bit representing asuccessive one of the bits in the quotient of the polynomial divisionperformed on the m×n contents of the ROM 10'. Previously, the bits ofthe quotient string have been discarded. However, in accordance with thepresent invention, the bits in the quotient string produced during thesecond polynomial division during step 30' are in fact utilized toincrease the effective size of the signature of the MISR 18 from n bitsto m+n-1. By doing so, the likelihood of error masking is eliminated.

Referring to FIG. 2, as the n bits in each row of the ROM 10' areshifted into the MISR 18', the bit output by the flip-flop 20'_(n)(representing a successive one of the quotient bits) is input to theexclusive OR gate 22'_(n). The exclusive OR gate 22'_(n) exclusivelyOR's or compacts each quotient bit with a successive one of the bitsstored in the n+1^(th) column of the ROM 10'. Recall that the n+1^(th)column of the ROM 10' was loaded with the quotient string generated atthe completion of the third stage polynomial division during which them×n contents of the ROM 10 were divided by the polynomial P₂. Alsorecall that at the completion of the third stage polynomial division,the resultant residue was a string of all zeros.

Since the polynomial divisor P₂ used during the third stage polynomialdivision is identical to the polynomial divisor used by the MISR 18'during step 32', a match should occur between each bit of the quotientstring stored in the n+1^(th) column of the ROM 10' and each bit of theactual quotient string produced during the second polynomial divisionwhen the residue in the MISR 18' is all zeros. Recall that a residue ofall zeros is the expected result when no errors in the ROM 10 arepresent because of the manner in which the initial seed loaded into theMISR 18' is calculated during step 28' of FIG. 3. Thus, the actualquotient associated with the all-zero residue should match the quotientobtained during the third stage polynomial division (step 28') which isloaded in the n+1^(th) column of ROM 10'.

Detection of whether a string of zeros results when the bits of thequotient string in the n+1^(th) column in the ROM 10' are exclusivelyOR'd with the quotient string obtained during the second polynomialdivision of step 32' is accomplished with the aid of the OR gate 23'.The OR gate 23' acts as a "1's" detector by OR'ing the current output ofthe flip-flop 20'_(n+1) with the output of the exclusive OR gate22'_(n). If, during any cycle of the second polynomial divisionperformed during step 32', the exclusive OR gate 22'_(n) has output a"1," the flip-flop 20'_(n+1) becomes set. In this way, a "1" is returnedto the input of the OR gate 23' so that a "1" appears at the output ofthe flip-flop 20'_(n+1) when a "1" is present in the actual quotientobtained during the second polynomial division of step 32'.

The process of exclusively OR'ing or compacting the quotient bits storedin n+1^(th) column of the ROM 10' with the quotient bits produced duringthe second polynomial division effectively increases the size (length)of the residue in the MISR 18'. At the end of the second polynomialdivision, the flip-flops 20'₁, 20'₂, 20'₃ . . . 20'_(n) contain the MISR18' residue, which is thus n bits long. However, the true length of theMISR 18' is actually n-1 bits because of the one-bit offset which occursduring each cycle of the polynomial division. The effective length ofthe residue obtained after the second polynomial division executedduring step 32' of FIG. 3 becomes n+m-1 bits, by virtue of exclusivelyOR'ing each quotient bit with each stored quotient bit in the n+1^(th)column of the ROM 18'. The increase in the effective size of the MISR18' residue means that none of the errors in the ROM 10' are lost(masked) during signature analysis.

Referring to FIG. 3, following the completion of the second polynomialdivision during step 32', the residue which remains in the MISR 18' isshifted out for analysis (step 34'). When no errors are in fact present,the resultant residue should be a string of all zeros since the initialseed loaded into the MISR 18' during step 28' was selected to yield justsuch a result after performing the first and second polynomial division.Thus, by examining the residue shifted out of the MISR 18', adetermination can be made whether the ROM 10' contains any errors.

As described, the present self-testing technique affords the advantageof effectively increasing the size of the MISR 18' residue whicheliminates the liklihood of error masking. Another advantage of thepresent technique is its reduced susceptibility to error cancellation.Such reduced susceptibility to error cancellation results fromsubjecting the m×n contents of the ROM 10' to both a first and secondpolynomial division performed by shifting bits in each successive row ofthe ROM into the MISR 18 in a first direction (left-to-right) and then asecond direction (right-to-left), respectively. Referring to Table I,when a first polynomial division is performed on the contents of the ROM10 of FIG. 1, error cancellation can occur because an erroneous bit inone row may be cancelled by a diagonally adjacent erroneous bit in thenext successive row. However, when a second polynomial division iscarried out by successively shifting the bits in each successive row ofthe ROM 10' into the MISR 18' in the opposite direction, the erroneouspair of bits which were diagonally adjacent during the first polynomialdivision is no longer diagonally adjacent as seen in Table II.

                  TABLE II                                                        ______________________________________                                                          0   1    1   0    1   1    0   1    1                                  0      0   1    0   1    .0. 1    0   1                                 0     1      0   0    0   1    0   1    0                                0    1     1      .0. 0    1   0    1                                         0    1     0       -1 0    0   0     -1 0    0   0    1                       ______________________________________                                    

Thus, the present self-testing technique, which is carried out byperforming two separate polynomial divisions in opposite directions, ismuch less susceptible to error cancellation.

The present self-test technique can easily be "built-in" (i.e.,incorporated) into the structure of a ROM, such as the ROM 10', in thesame way that the conventional signature analysis technique may beincorporated. To incorporate the present technique, the number ofstorage cells must be expanded to include an extra column to store a setof predetermined quotient bits. Secondly, the MISR 18 of FIG. 1 must bereplaced with the MISR 18' of FIG. 2. Lastly, two separate polynomialdivisions are required.

It is to be understood that the above-described embodiments are merelyillustrative of the principles of the invention. Various modificationsand changes may be made thereto by those skilled in the art which willembody the principles of the invention and fall within the spirit andscope thereof.

I claim:
 1. A method for self-testing a read-only memory (ROM)configured of an m row by n+1 column array of single-bit storage cells,where m and n are integers, the n+1^(th) column containing a set ofpredetermined bits, comprising the steps of:performing a firstpolynomial division on the m×n+1 bits stored in the ROM by inputting then+1 bits in each successive row of the ROM to a bidirectional multipleinput shift register (MISR) initialized with a predetermined seed andshifting said n+1 bits in each successive ROM row through the MISR in afirst direction; performing a second polynomial division on the first nbits in each of the m rows of the ROM by inputting n bits in eachsuccessive row of the ROM into the MISR and shifting said n bits throughthe MISR in a second opposite direction, such that at the completion ofthe second polynomial division, a residue remains in the MISR;simultaneously generating a quotient bit in the MISR as each of thefirst n bits in each successive row of the ROM are shifted in the seconddirection through the MISR; logically combining each successive one ofthe quotient bits generated by the MISR with a separate one of thepredetermined bits stored in the n+1^(th) column of the ROM; detectingif a bit of a preselected state results when each separate bit in then+1^(th) column of the ROM is logically combined with each separatequotient bit generated by the MISR, and if so, then indicating an errorin the ROM; and examining the residue remaining in the MISR after thesecond polynomial division to detect the presence of an error in theROM.
 2. The method according to claim 1 wherein prior to performing thefirst polynomial division, the MISR is initialized with a seed which isselected such that at the completion of the first and the secondpolynomial division, the residue remaining in the MISR consists of allzeros when no errors in the ROM are present.
 3. The method according toclaim 2 wherein the seed is established by the steps of:performing afirst stage polynomial division on a dividend consisting of the contentsof ROM (excluding the n+1^(th) column) using a first polynomial divisor(P₁) and using an initial seed of all zeros, the first stage polynomialdivision yielding a residue S₁ ; performing a second polynomial divisionon a dividend of all zeros using a divisor polynomial P₂ equal to thereciprocal of P₁ and using an initial seed equal to S₁, the secondpolynomial division yielding a residue S₂ ; performing a third stagepolynomial division on a dividend consisting of the contents of the ROM(excluding the n+1^(th) column) using the polynomial P₁, the thirdpolynomial division yielding a quotient string q and a residue S₃ ;performing a fourth stage polynomial division on the entire contents ofthe ROM using a third polynomial divisor P₃ and seed of all zeros, thefourth polynomial division yielding a residue S₄ ; and performing afifth stage polynomial division on a dividend of all zeros using apolynomial divisor P₄ equal to the reciprocal of P₃ and a seed obtainedby logically OR'ing the residues S₂ and S₄, the fifth stage polynomialdivision yielding the initial seed for the MISR.
 4. The method accordingto claim 3 wherein the quotient string stored in the n+1^(th) column ofthe ROM is the quotient string produced at the completion of the thirdstage polynomial division.
 5. The method according to claim 1 whereinthe bits stored in the n+1^(th) column of the ROM are precalculated suchthat when each bit is logically combined with a corresponding one of thequotient bits generated by the MISR, the resultant bit is a zero. 6.Apparatus for self-testing a ROM containing an m row by n+1 columnmatrix array of single bit storage cells, the n+1^(th) column of the ROMcontaining a predetermined quotient string, the apparatuscomprising:counter means for addressing each row of the ROM to cause thebits stored in each row to be shifted out; bidirectional multiple inputshift register (MISR) means for: (a) performing a first polynomialdivision on the bits stored in the entire m×n+1 array of ROM storagecells as the bits are shifted out from the ROM and through the MISRmeans in a first direction; (b) performing a second polynomial divisionon the bits stored in an m×n array within the m×n+1 array of ROM storagecells as the bits in each of the first n columns of each row are shiftedthrough the MISR means in a second direction, and generating a residuefollowing such division; (c) producing a quotient bit as each of the nbits in each successive row is shifted through the MISR during thesecond polynomial division; (d) logically combining each successivequotient bit with a separate one of the bits stored in the n+1^(th)column of the ROM; and (e) detecting whether each bit resulting from thelogical combination of the produced quotient bit and the stored quotientbit is of a predetermined state; and means for comparing the residuegenerated after the second polynomial division with a known goodresidue.
 7. The apparatus according to claim 6 wherein the MISR meanscomprises:n+1 flip-flops f₁, f₂,f₃ . . . f_(n+1), each having an inputand an output; a set of multiplexers m₁,m₂,m₃ . . . m_(n+1), each of themultiplexers m₁,m₂,m₃ . . . m_(n-1) having a first input coupled to theoutput of a separate one of the flip-flops f₁,f₂,f₃ . . . f_(n-1) and asecond input coupled to the output of a separate one of the flip-flopsf₃,f₄,f₅ . . . f_(n+1), and an output, the multiplexer m_(n) having afirst input, a second input, and an output, the output coupled to theinput of the flip-flop f_(n+1), the multiplexer m_(n+1) having a secondinput coupled to the output of the flip-flop f₂, and a first inputsupplied with a feedback signal from the selected set of the flip-flopsf₁,f₂,f₃ . . . f_(n+1) ; a set of exclusive OR gates o₁,o₂,o₃,o₄ . . .o_(n+2), each of the first n-1 gates o₁,o₂,o₃,o₄ . . . o_(n-1) having afirst input coupled to the output of a separate one of the multiplexersm₁,m₂,m₃ . . . m_(n-1), respectively, a second input supplied with aseparate one of the bits stored in the second through the n^(th) columnsof a successive row of the ROM as they are shifted out of the ROM, andan output coupled to the input of a separate one of the flip-flopsf₂,f₃,f₄ . . . f_(n), respectively, the gate o_(n) having a first inputsupplied with the output signal of the flip-flop f_(n), and a secondinput supplied with the bit stored in the n+1 column of a successive rowof the ROM, and an output, the gate o_(n+1) having a first inputsupplied with the output of the multiplexer m_(n+1), a second inputsupplied with the bit stored in the first column of a successive row ofthe ROM as the bit is shifted out of the ROM, and an output coupled tothe input of the flip-flop f₁, the gate o_(n+2) having a first inputsupplied with a feedback signal of the selected flip-flops f₁,f₂,f₃ . .. f_(n), a second input supplied with a separate one of the bits of then+1^(th) column of the ROM, and an output coupled to the second input ofthe multiplexer m_(n),; and an OR gate having a first input suppliedwith the output of the exclusive OR gate o_(n), a second input suppliedwith the output of the flip-flop f_(n+1) and an output supplied to thefirst input of the multiplexer m_(n).